This invention relates to digital signal processing devices and, more particularly, to digital filters.
A digital filter is a device which operates digitally on digital representations of an analog signal that is sampled at specific instances of time. In an overall filtering process, an analog-to-digital converter periodically samples the analog signal and encodes the sample into digital signals. A digital filter then processes the digital signals, after which the processed digital signals are converted back to the analog signal by a digital-to-analog converter. In accordance with the well-known sampling theorem, the sampling frequency must be equal to or greater than twice the highest frequency component of the analog signal being sampled to reconstruct the analog signal with all of its frequency components and without distortion due to aliasing. Digital filters, in general, have many advantages over analog filters, such as cost and the ability to realize filter functions that are difficult to realize in the analog domain.
Digital filters typically are constructed of logic devices such as multipliers and adders, and respond to a clock frequency signal which is used to process the digital signals through the filters. Digital filters can have a non-recursive portion, in which the output signals are not fed back to the input, and a recursive portion, which processes the output signals fed back to the recursive portion, to perform the filtering functions. The maximum clock frequency, and hence maximum speed of the digital filters, is limited by the physical delays introduced by such logic devices and the complexity of the filtering function being implemented. The longer the physical delays introduced by a particular multiplier or adder, and/or the greater number of logic devices needed to implement a more complex function, i.e., the more complex the logic design, the lower the clock frequency.
In a given overall filtering process, the clock frequency equals the sampling frequency and, ideally, both are identical to the theoretical sampling frequency. However, if the analog signal has very high frequency components, the limitations imposed by the construction and complexity of the digital filters usually prevent achieving a clock frequency as high as the theoretical rate. Consequently, the sampling frequency may have to be reduced below the theoretical sampling frequency because of the maximum clock frequency of the digital filters. Alternatively, the sampling can occur at the theoretical rate, but high speed filtering cannot be serviced. Thus, digital filters may have the disadvantage of preventing reconstruction of the analog signal with all of its frequency components.
Two approaches to reducing this problem are using multipliers and adders which produce less physical delay in processing the digital signals and/or simplifying the logic design implementing the filtering function. The former may not be likely due to the state-of-the-art of these devices, and the latter may not be possible or may be extremely difficult.